The present invention relates to a control system for a vector processor having a plurality of pipelined processing units, and more particularly to a control system suitable for synchronizing or serializing at high speed vector instructions to be processed by the pipelined processing units.
For a vector processor having a plurality of pipelined processing units, it is necessary to synchronized or serialize (hereinafter generally called serializing) vector instructions to be processed at each pipelined processing unit in order to ensure the order of reference to a main storage. Specifically, in a case where a plurality of main storage reference instructions can be executed at the same time, such serialization becomes necessary for execution of succeeding access instructions after completion of advancing access instructions.
As a means for realizing such process, there is known a process as disclosed, e.g., in JP-A-59-125472. According to this publication, a POST flag is provided for each pipelined process stage. When a POST instruction (a kind of serialization instruction) is executed, the POST flag is set at a corresponding process stage where an access instruction is being executed. The POST flag is moved from one stage to another as the processing advances. As another means for serialization, there is known a process as disclosed, e.g., in a publication "HITAC S-810 Processor" at page 60. According to this publication, a VWAC instruction for suspending all the pipelined processing is provided wherein only an access instruction to a main storage is taken into consideration in such a manner that a VWAC instruction is repeatedly executed so as to inhibit execution of succeeding instructions until all the main storage access instructions of advancing instructions before the VWAC instruction have been completed.
Such conventional technique for serialization relies on a concept that succeeding instructions after a serialization instruction are inputted to pipelined processing units only after advancing instructions have been executed fully in the pipelined processing units.
However, the time when serialization of instructions is required actually is at a stage of accessing a main storage, taking an access instruction as an example. At the preceding pipelining stages, it is possible to execute the instructions irrespective of serialization. In other words, in a conventional method of inputting succeeding instructions to pipelined processing units after the advancing instructions have been fully executed, time is wasted on the processings at stages not associated with serialization.